Skip to content

Trailing Edge Tech Geeking

Over the past couple of weeks, I have been obsessed with a YouTube play list by Ben Eater. In it, he describes building a simple 8-Bit computer on a very large breadboard. He has additional information, including parts lists both for the entire project and each component, on his website. I had become interested in building a TTL CPU after reading about the Gigatron project and devoured the videos.

In the last video of the series, Ben describes additions people have made while watching the video such as expanded address space and additional instructions. He mentions one, optimizing instruction execution by using an available control line to reset the instruction decoder’s counter, that I had considered. He later used it for conditional jumps to make the machine Turing complete.

I am in the process of obtaining parts to follow along and build with the series. While I am waiting, I have two ideas for carrying on after it I complete the initial version. The first takes off in a different, but current direction. The second looks back to the past for something very unconventional in the contemporary era.

The more conventional path is to expand the register set and change the instruction set type. Instead of one accessible accumulator, his register A, and one register used not visible to a programmer, his register B, it would use eight general-purpose registers. To work with them, it would use a load/store architecture instead of the register memory architecture in the original design. This design is typical in modern RISC machines. It also makes it possible to create instructions of almost uniform size. In my paper design, the only three byte instructions are those that move data between a register and a memory location and the various jump instructions. I can expand it by using 256-byte pages and all memory access using the current page. This would require adding a page set (PGS?) instruction which would also be two bytes, one opcode, and a page number. Like some architectures with composite memory addresses it could set multiple page indexes, such as a data page and a program page. This idea, with the pages called fields, is used by the PDP–8 in later models which had a maximum memory of 32K words.

Speaking of the PDP–8 that is my second, less conventional, expansion. The PDP–8, introduced in 1965, has an architecture from the end of the word-oriented computer era and used 12-bit words. While the System/360 would be the system that ushered in the byte addressable world of computers today, IBM only introduced it the prior year and shipped it a little later than the PDP–8. It would take a while for the modern world of byte addressing, standardized eight-bit bytes, and multiple bytes words to become universal. While Digital, makers of the PDP–8, introduced the last computer of their 18-bit word line in 1970, the last of their 36-bit line launched in 1977 and the final 12-bit machine, the DECmate III+ line of microcomputers which used the same instruction set as the PDP–8, saw life in 1985.

Beyond the odd word size at 12 bits the other thing that would make the PDP–8 an intriguing path for Ben’s computer is the instruction set. It only used the top three bits of the word for the op-code. Instructions 00 through 05 use the next two bits to set an addressing mode and the lower seven bits in constructing the address. Instructions 06 and 07 use the lower bits to do a variety of IO operations and processing ,respectively. The instruction set itself is unusual. You can AND the contents of a memory address with the accumulator, do twos complement addition of memory contents with the accumulator, increment a memory location and skip the next instruction if the result is zero, save the accumulator to memory and clear the accumulator, and do two jumps, one to a subroutine and one unconditional.

Ignoring the IO operations, in the 07 instruction you can do a combination from one of two sets. The first set is clear the accumulator, clear the Link bit (think Carry, although it does more than that), ones compliment the accumulator or link bit, increment the accumulator, and rotate the combined accumulator/link bit one or two rotations left or right. The second set provides various conditional skips (but not jumps), clear the accumulator, load the front panel switches into the accumulator or halt the machine. What is interesting is the machine performs bit instructions in bit order so if you use set one and clear the accumulator, increment, and rotate left twice the result is an accumulator value of 0004.

Implementing this instruction set would be a fun and very educational project. If I get ambitious a significant amount of PDP–8 binary code can is available on the web. If I can find a way to to load it into the breadboard machine, I could test my implementation against actual software from out in the world. If I let ambition fly, I can see in a year or two having my version of the architecture, an HDP–8 (Herb’s Data Processor–8 or maybe make that a 12 for 12-bit), running OS8 as I do with SimH right now.

Will I get that far? Who knows. For now, I want to get the machine in the videos running. Then I will examine where to go next.

Note: this post was updated on 2018-08-10. The two PDP-8 front panel images were added. The video link was moved from between the second and third paragraphs to between the first and second paragraph. Also, tags were added.

Published inUncategorized

One Comment

Leave a Reply

Your email address will not be published. Required fields are marked *

This site uses Akismet to reduce spam. Learn how your comment data is processed.

Social Media Auto Publish Powered By : XYZScripts.com